UVM-SystemC Randomization Workshop @ DVCon US 2021
UVM-SystemC Randomization Workshop @ Design & Verification Conference United States 2021
March 1-4, 2021
By: Thilo Voertler, COSEDA Technologies GmbH
Dragos Dospinescu, AMIQ
Contributions to the short workshop presentation are also provided by:
Martin Barnasconi, NXP Semiconductors
Stephan Gerth, Bosch Sensortec GmbH
This workshop will introduce the basic concepts of UVM-SystemC and show how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the Accellera VWG is working on the standardization of a common randomization layer based on CRAVE, a C++, and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.