COSEDA @ DVCon Japan 2026

Design & Verification Conference JAPAN 2026

The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.

Tutorial @ DVCon Japan 2026: SystemC / SystemC AMS - Virtual Prototyping for complex heterogenous systems

Presented by COSEDA Technologies in collaboration with Siemens EDA & Universität zu Lübeck

Speakers: Thilo Vörtler & Karsten Einwich (COSEDA Technologies GmbH, Germany)

The increasing complexity of integrated electronic systems, especially due to the more and more used chiplet technology, make the usage of virtual prototypes essential. Virtual prototypes offer several advantages. They provide an executable platform that improves communication between stakeholders across the value chain. They enable different design activities - such as software development, analog/digital design, and test development - to start earlier and run in parallel. In addition, they support specification validation through the execution of application scenarios and improve verification quality by providing a reference model.
The tutorial will demonstrate the usage of the IEEE SystemC and SystemC AMS modeling standards for the development of virtual prototypes of heterogenous systems consisting of digital hard- and software as well as analog subsystems and an analog digital environment.

The presentation will start with a motivation for virtual prototyping by introducing different use cases starting with executable specification/concept development, design space exploration, hardware/software co-design to the reference model for implementation level verification.

Afterwards, the usage of different model of computation will be introduced and illustrated by examples. Thereby, system level modeling techniques will be explained and discussed. Different real-life example will be presented and used to demonstrate the possibilities and power of SystemC and SystemC AMS based virtual prototyping. The tutorial will end with a sneak preview to the next SystemC AMS standard update and present the new upcoming features and their use cases.

We are looking forward to meet you in Yokohama Kangawa, Japan.