psd
Project Library Model Name Kind
pll libpll psd Hierarchical Module

Ports

Name Interface Type Description
clk_ref sc_core::sc_in bool reference clock
clk_div sc_core::sc_in bool divided output frequency
up sc_core::sc_out bool up output
dn sc_core::sc_out bool down output

Description

PFD implementation

Schematic

d_i clk_i rst_i q_o i_dffrst_sc1 <bool> rst_value = false posedge = true RST DFF i_const_src_sc1 <bool> const_val = true CONST_SRC_SC<T> clk_ref IN clk_div IN up OUT dn OUT i_const_src_sc2 <bool> const_val = true CONST_SRC_SC<T> sc0_i sc1_i sc_o <bool, bool> i_and2_reduced_sc & REDUCED d_i clk_i rst_i q_o i_dffrst_sc2 <bool> rst_value = false posedge = true RST DFF reset
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(customizable in sca_modules.dtd)