psd_tb
Project Library Model Name Kind
pll libpll psd_tb Hierarchical Module

Parameters

Name Type Default Description
ref_clk_period double 1e-6 Reference clock period
div_clk_period double 1.01e-6 Divided clock period
delay double 10e-9 Phase detector delay

Description

Phase Frequency Detector test bench

Long Description

Enter the module documentation here.
It will be inserted into the generated modul documentation (SystemC-AMS Tools Create Documentation)

Schematic

ref_clk_period = 1e-6 div_clk_period = 1.01e-6 delay = 10e-9 clk_ref clk_div up dn i_psd PSD clk_o i_std_clock_sc1 period = sca_time(p.ref_clk_period, SC_SEC) duty_cycle = 0.5 start_time = sc_core::SC_ZERO_TIME posedge_first = true STD_CLOCK_SC t 1 clk_o i_std_clock_sc2 period = sca_time(p.div_clk_period, SC_SEC) duty_cycle = 0.5 start_time = sc_core::SC_ZERO_TIME posedge_first = true STD_CLOCK_SC t 1 clk_ref clk_div up dn
@copyright COSEDA Technologies GmbH. All rights reserved.
(customizable in sca_modules.dtd)