PLL Example for COSIDE® (by Americo Dias)

Start Simulation

The simulation can be started by executing: pll/libpll/Binaries/top_simple_tb.exe (for further details click on the image below).

Model Overview

The building blocks of the PLL, their connection and their simulation domains are shown in the following picture.

(click on the image above to navigate Phase Locked Loop Simulator in SystemC-AMS by Americo Dias)

(click on the image above to navigate to the model documentation)

Short Description

The Phase Frequency Detector (PFD) compares the phase of the reference clock with the phase of the feedback signal. If the phase of the reference clock is ahead of the feedback signal, it will "tell" the charge pump to "go faster". If the feedback signal is ahead instead, will "tell" to "go slower". Using these up/down signals, the Charge Pump (CP) generate pulses of positive or negative current. This current is applied to the Loop Filter (LF), which integrates it and generates the control voltage that is applied to the Voltage Controlled Oscillator (VCO) and defines the frequency of the output. The Frequency Divider takes the output signal and divides its frequency by a predefined factor, generating the feedback signal that is compared with the reference clock. (quote: Americo Dias)

Simulation Result

Below the expected simulation results are displayed: