phase_detector_tb
Project Library Model Name Kind
pll libpll phase_detector_tb Hierarchical Module

Parameters

Name Type Default Description
ref_clk_period double 1e-6 Reference clock period
div_clk_period double 1.3e-6 Divided clock period
delay double 10e-9 Phase detector delay

Description

hierarchic symbol

Schematic

clk_o i_clock_src_sc1 <bool> high_level = {T}(1) low_level = {T}(0) period = sca_time(p.ref_clk_period, SC_SEC) start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level clk_o i_clock_src_sc2 <bool> high_level = {T}(1) low_level = {T}(0) period = sca_time(p.div_clk_period, SC_SEC) start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level up dn clk_ref clk_div i_phase_detector_no_delay1 PHASE_DETECTOR_NO_DELAY clk_ref clk_div up dn i_phase_detector1 td = sca_time(p.delay, SC_SEC) PHASE_DETECTOR ref_clk_period = 1e-6 div_clk_period = 1.3e-6 delay = 10e-9 clk_ref clk_div up_nd dn_nd dn up